產(chǎn)品特點(diǎn)及安裝說明
Description
The 1-Gbit DDR2 SDRAM is a high-speed Double-Data- Rate- Two CMOS Synchronous DRAM device Containing 1,073,741,824 bits and internally configured as an octal bank DRAM.
The 1-Gbit device is organized as 16 Mbit ×8 I/0 ×8 banks or 8 Mbit ×16 1/O ×8 banks chip. These synchronous devices achieve high speed transfer rates starting at 400mb/sec/pin for general applications.
The device is designed to comply with JEDEC DDR2 DRAM Standard key features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.
A 14 bit address bus for x8 organised components and a 13 bit address bus for x16 components is used to convey row, column and bank address information in a RASCAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
The DDR2 SDRAM is available in TFBGA package.
Features
The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:
? 1.8 V ±0.1 V Power Supply
1.8 V ±0.1 V (SSTL_18) compatible I/O
? DRAM organizations with x8, ×16 data in/outputs
? Eight internal banks for concurrent operation
? Programmable CAS Latency: 3, 4, 5, 6, 7
? Programmable Burst Length: 4 and 8
? Differential clock inputs (CK and CK)
? Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data.
? DLL aligns DQ and DQS transitions with clock
? DQS can be disabled for single-anded data strobe operation
? Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
? Data masks (DM) for write data
? Posted CAS by programmable additive latency for better command and data bus efficiency · Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality· Auto-Precharge operation for read and write bursts
? Auto-Refresh, Self-Refresh and power saving Power- Down modes
? Operating temperature range (TcASE)
- Commercial, (0 ℃ to 95 ℃)
- Industrial, I (-40 ℃ to 95 ℃)
-Automotive grade 3,A3(-40 ℃ to 95 ℃)
? Average Refresh Period 7.8 us at a TcAsE lower than 85 ℃.3.9 us between 85 ℃ and 95 ℃
? Programmable self refresh rate via EMRS2 setting
? Full and reduced Strength Data-Output Drivers
? 1KB page size for ×8, 2KB page size for ×16
? Packages: PG-TFBGA-60 for x8 and PG-TFBGA-84 for ×16
